With transistor dimensions continuously shrinking, short channel effects (SCE), poly gate activation, and junction capacitance become critical issues in MOS device design. For transistors manufactured with a narrow spacer scheme, post gate doping and graded source/drain energy need to be reduced to maintain an acceptable SCE control. This results in poly depletion effects and high junction capacitance. With a conventional single-spacer process, it is hard to achieve improved short channel effect, good poly gate activation, and lower junction capacitance simultaneously. Particularly, in order to reduce the hot carrier effect, lightly doped drains (LDD) are increasingly used close to the channel. However, this causes higher sheet resistance between the source/drain regions and the channel region and thus low drain saturation current due to low impurity concentration.
What is needed in the art is a method for manufacturing semiconductor devices that does not suffer from the deficiencies of conventional techniques. The method can be implemented by using multiple spacers and slim spacers.